The present disclosure relates to a semiconductor memory device, and more particularly to an internal voltage generation device.
In general, a semiconductor memory device receives a supply voltage VDD, and generates and uses internal voltages required within a chip, including a core voltage Vcore and a high voltage VPP. The core voltage Vcore is used in a core area of the memory device, and is generated by down-converting the supply voltage VDD. The high voltage VPP is used to drive word lines of the memory device, and is generated by boosting the supply voltage VDD.
Meanwhile, an amount of refresh current consumption becomes an important issue in a dynamic random access memory (DRAM). A refresh operation of the DRAM includes an auto-refresh mode and a self-refresh mode. In each mode, word lines are refreshed in the order of internally controlled addresses at a certain period corresponding to a refresh retention time of each cell.
The self-refresh mode is an operation mode where the DRAM internally performs the refresh operation by itself for retention of information stored therein when a system including the DRAM carries out no operation for a certain period of time. For this reason, the DRAM consumes a large amount of current in the self-refresh mode.
One approach to reducing current consumption in the self-refresh mode which is called a multi-word line refresh technique, is to refresh cells connected to two or more word lines at the same time while the refresh operation is performed once and control a refresh period to twice or more of the refresh period of a conventional approach.
Application of the multi-word line refresh technique makes it possible to reduce the amount of current to be used in a refresh control circuit as compared with that when cells are refreshed one by one.
However, application of the multi-word line refresh technique to a DRAM is disadvantageous in that there is a shortage of driving capabilities of internal voltages used for refresh operation as DRAM capacity increases.